搜索资源列表
spi_verilog
- 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
ADC_AMP
- VHDL code for ADC on Spartan 3E starter kit
FPGA_SPI_controller
- 基于FPGA的SPI协议控制器的设计，主要针对主控制器的设计，采用VHDL语言编写的。-The SPI protocol controller based on FPGA design, mainly for the design of the main controller, using VHDL language.
spi
- vhdl spi pin configuration
spi.asm
- vhdl spi port configuration
spi.sim
- vhdl spi cpld simulation
spi
- 基于CPLD的用SPI控制pwm的源码，用VHDL编写，已经测试，可以直接使用
SPIVerilogHDL
- SPI协议Verilog HDL程序包用Verilog语言实现fpga模拟实现spi协议功能-fpga-spi-verilog
SPI
- 利用VHDL实现spi，IPcode 的 spi-Using VHDL implementation spi, IPcode the spi
Verilog000
- FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。-Verilog语言的学习，熟悉Verilog语言的各种语法。 ②、FPGA的学习，熟悉
l1ghVhVI
- The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
SPI_verilog_vhdl
- spi接口的VHDL和Verilog-HDL源码-VHDL and Verilog-HDL code for spi
FPGA_SPI.ZIP
- 实现了FPGA以SPI协议传送和接受16位数据。传送过程无需Nios核干预-SPI protocol to achieve the FPGA to send and receive a 16-bit data. Nios nuclear transfer process without intervention
VHD_Veri_spi
- 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequen
spi_write
- 对spi接口的flash操作，用VHDL语言实现，read，write，擦除的接口电路控制-Spi interface on the flash operation, with the VHDL language, read, write, erase controls the interface circuit
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
VHDL-based-design-of-SPI
- 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous comm
SPI_interface(VHDL)
- SPI接口模块源代码（VHDL）语言，经过产品应用测试。-SPI interface module source code (VHDL language), after product application testing.
spiflash
- VHDL language to read and write of the SPI FLASH
CoreSPI_21_eval
- SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages Verilog and VHDL source code